A conventional nonvolatile semiconductor memory device includes an electrically erasable and programmable nonvolatile memory (flash EEPROM) including a memory cell array in which memory cells each having an electrically insulated floating gate are arranged in row and column directions in the form of a matrix (refer to non-patent document 1, for example). In addition, the conventional nonvolatile semiconductor memory device includes a nonvolatile memory having a virtual ground line type memory cell array constitution (refer to patent documents 1 to 3, for example). Here, FIG. 3 is a sectional view showing a virtual ground line type memory cell array including a memory cell having a floating gate structure, viewed from a direction perpendicular to a bit line.
As shown in FIG. 3, according to this memory cell array, memory cells 2 and 3 including a tunnel insulation film 8, floating gates 4 and 5 and an insulation film 9 are formed on a first conductivity type semiconductor substrate 7. The gates of the two adjacent memory cells 2 and 3 are connected to the same word line 1. A diffusion region 6b is provided in a self-aligned manner on the semiconductor substrate 7 below an interval part A between the floating gate 4 of the memory cell 2 and the floating gate 5 of the memory cell 3. In addition, diffusion regions 6a to 6d formed between the floating gates function as bit lines connected to the drain and source of each memory cell. Thus, since it is not necessary to provide a contact to connect the source and drain of the memory cell to a metal wiring, at the interval A with respect to each memory cell, the dimension of the interval part 6 can be reduced.
The floating gate 4 is electrically insulated by the insulation film from the terminals such as the control gate, source, drain and channel positioned around the floating gate 4, and the potential of the floating gate 4 is controlled by capacity coupling from these terminals. According to a data programming action, similar to a programming principle of a UV erase type EPROM, an electron is injected into the floating gate 4 by applying energy enough for exceeding a barrier height of the tunnel insulation film 8 serving as the insulation film, to the electron based on a hot carrier phenomenon as a mechanism. According to an erasing action, the electron is discharged through the tunnel oxide film 8 of the overlapped region of the floating gate 4 and the semiconductor substrate 7 based on a Fowler-Nordheim tunnel phenomenon as a mechanism. Thus, the number of the electrons in the floating gate 4 is adjusted. A reading action is performed, similar to a NOR type memory including a normal MOS transistor, by sensing a difference in accumulated data (electron number) of a drive current of the memory cell selected by the bit line 6b and the word line 1.
The programming action of the memory cell 3 by the hot carrier phenomenon is performed by applying a program row voltage VWP to the word line 1 serving as the control gate of the memory cell 3, applying a program column voltage VBP to the bit line diffusion region 6b serving as the drain of the memory cell 3, and applying a ground voltage to the bit line diffusion region 6a serving as the source of the memory cell 3. Thus, a channel hot electron induced by a channel current of the floating gate 5 of the memory cell 3 is generated in the vicinity of the end part of the diffusion region 6b under the floating gate 5, and injected in the floating gate 5 by an electric field generated by the program row voltage VWP applied to the word line 1 serving as the control gate. At this time, since the bit line diffusion regions 6b and 6c are fixed to the same potential, a channel current enough for injecting a hot electron to vary the threshold voltage of the memory cell 2 does not flow in the floating gate 4 of the unselected memory cell 2. Thus, the threshold voltage of the memory cell 2 is not varied.
FIG. 2 is a circuit diagram showing the array constitution of the virtual ground line type memory cell array. The memory cell array includes word lines WLi (i=0, . . . , k, k+1, . . . ) connected to a row decoder and bit lines BLj (j=0, . . . , m, . . . , n) connected to a column decoder, in which the control gates of the memory cells belonging to the same row are connected to the same word line, the sources and drains of the memory cells belonging to the same column are connected to one adjacent pair of bit lines, and the bit line is shared by the two adjacent memory cells in the row direction. According to the example shown in FIG. 2, the memory cell array is divided into a plurality of blocks in the row direction every n bit lines, and regions 1a and 1b for isolating the electrical connection between the memory cells is provided between the adjacent blocks.
Referring to FIG. 2, bit line number on the right side (drain side, for example) is “m” and a bit line number on the left side (source side, for example) is “m−1” out of the two bit lines adjacent to the memory cell having an address “m”.
The programming action for the selected memory cell [k, m] is performed by applying the program row voltage VWP to the word line WLk connected to the gate of the selected memory cell [k, m], grounding the bit line BLm−1 connected to the source thereof and applying the program column voltage VBP to the bit line BLm connected to the drain thereof. The program row voltage VWP is a high voltage such as 9 to 12V in general and the program column voltage VBP is 4 to 6V to generate hot carriers in the selected memory cell [k, m] sufficiently. In addition, at this time, the program column voltage VBP is applied to all the bit lines on the drain side of the selected memory cell [k, m], that is, to the bit lines BLm to BLn, and all the bit line on the source side of the selected memory cell [k, m], that is, the bit lines BL0 to BLm−1 are grounded. Thus, a voltage difference between the drain and source of the unselected memory cell other than the selected memory cell is prevented from being generated in the memory cell array having the virtual ground line type array constitution, whereby undesired parasitic programming (referred to as the program disturb hereinafter) is prevented from being generated in the unselected memory cell. Thus, the programming action is implemented for the selected memory cell [k, m].
Furthermore, the nonvolatile memory having the virtual ground line type memory cell array constitution includes a nonvolatile memory having a memory cell array not provided with a floating gate, as another conventional example (refer to patent document 4, for example). Here, FIG. 7 is a sectional view showing the nonvolatile memory viewed from the direction perpendicular to the bit line, in which a silicon nitride film layer 4b is used instead of the floating gate 5 in the example of the nonvolatile memory shown in FIG. 3, to retain an electric charge.
Patent document 1: Japanese Unexamined Patent Publication No. 2003-187584
Patent document 2: Japanese Unexamined Patent Publication No. 04-230079
Patent document 3: Japanese Unexamined Patent Publication No. 03-176895
Patent document 4: Japanese Unexamined Patent Publication No. 2000-514946
Non-patent document 1: S. Mukherjee et al., “A Single Transistor EEPROM Cell and implementation in 512 k CMOS EEPROM”, IEDM Technical Digest, pp 616, (1985)